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Ordering number : ENN8096A
SANYO Semiconductors
DATA SHEET
Silicon Gate CMOS IC
LC749450NW
Overview
Digital RGB Image Processor IC
The LC749450NW RGB image processing IC converts interlaced video signals such as NTSC and PAL to progressive scan and adjusts the image quality of that signal. Since the LC749450NW can operate at input clock frequencies up to 27 MHz, it is optimal as a pixel display device IC for high-quality high-resolution images. A high image quality progressive scan signal playback system can be implemented easily by combining the LC749450NW with external memory (two 16M SDRAMs).
Features
* * * * * * * * * * * * * * * * * * * * * * * * * Accepts 30-bit (4:4:4) YCbCr signals, 20-bit (4:2:2) YCbCr signals, and 10-bit RT.656 signals as inputs. Supports digital TV inputs (480i, 480p, 1080i, and 720p): 30-bit YCbCr digital signal input. 30-bit digital RGB signal inputs Produces 30-bit and 24-bit digital RGB (or YCbCr) signal outputs Provides both YCbCr/YPbPr RGB conversion and RGB YCbCr conversion Motion adaptive jaggy-less interlaced to progressive conversion 3:2 pull down Multiple noise reduction systems (1D, 2D, and 3D) Cross color and cross luminance cancellers Horizontal outline correction (LTI and CTI) Sharpness (horizontal and vertical) Sharpness adjuster (shading relief enhancement) White and black level expansion, white text correction (blue stretch) Flesh tone correction Hue and color gain adjustments Color exciter (6-phase RGBYMC independent saturation adjustment) Brightness and contrast adjustment White balance and black balance adjustment Gamma correction (Independent RGB, programmable LUT system) Dithering (10-bit and 8-bit) Clamp control Aspect ratio conversion (4:3 16:9) Clock generator (PLL) circuit SDRAM interface I2C bus and CPU interface circuits
SDPICTM: SANYO Digital Picture Improvement Core SDPICTM is a registered trademark of SANYO Electric Co., Ltd.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
70105HK OT B8-7981 No.8096-1/17
LC749450NW
Package Dimensions
unit : mm 3261
31.2 0.8 105 104 53 1 (0.5) (1.25) 0.2 52 (3.2) 0.15 28.0 156 157
208
SANYO : SQFP208J (28 x 28)
IC Specifications
* Supply voltage: Core block: 1.8 V, I/O blocks: 3.3 V * Maximum operating frequency: 27 MHz (IP conversion mode), 135 MHz (IP conversion not used) * Package: 208-pin SQFP
Main Applications
* LCD TVs, monitors, and projectors * PDP TVs and progressive scan TVs * DVD players and recorders
Functional Overview
1. Input signal formats The digital data port supports the following input signal formats. 30-bit RGB 30-bit (4:4:4) YCbCr/YPbPr 20-bit (4:2:2) YCbCr/YPbPr 10-bit signals conforming to the ITU-R BT.656 standard (horizontal and vertical sync inputs required) NTSC (480i/480p), PAL (576i/576p), and HD (1080i/720p) RGB (up to 135 MHz) 2. IP conversion block For NTSC (480i) and PAL (576i) inputs the LC749450NW provides motion adaptive IP conversion or cinema IP conversion (3:2 pull down) with both 2D/3D noise reduction and cross color/cross luminance cancellation. External SDRAM (either 2 x 16 Mbits or 1 x 64 Mbits) is required when the functions of this block are enabled. This block is set to bypass mode for 480p, 576p, 1080i, 720p, and PC (RGB) inputs. (1) Motion adaptive IP conversion The LC749450NW performs motion detection for each pixel that enters the IP conversion block. Based on that result, the block performs interlaced to progressive conversion. Pixels that are found to be static are interpolated between fields and pixels that are found to be moving are interpolated within the field. Since this circuit takes correlations in the diagonal directions into account when performing inter-field interpolation for moving sections of the image, it can create smooth video with minimal stair-stepping artifacts (jaggies). Furthermore, this function can handle images that range from relaxed smooth video to video with violent motion by setting parameters and changing the motion threshold values for each pixel.
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0.1
3.56max
28.0
31.2
LC749450NW
Continued from preceding page.
(2) Cinema mode IP conversion (3:2 pull down) When an NTSC interlaced signal that was generated by a film (cinema) source is input, it automatically recognizes the signal as a cinema source and performs cinema mode IP conversion that is optimal for cinema sources. The threshold value for that recognition can be set with a parameter. (3) Noise reduction (2D, 3D) The LC749450NW provides three noise reduction functions: 3D noise reduction, which reduces noise between fields, 2D noise reduction, which reduces noise within the field, and 1D noise reduction, which reduces noise in the scan line direction. This block contains the 3D and 2D noise reduction functions and can operate independently for both the luminance signal and the chrominance signal. (4) Cross color and cross luminance canceller This circuit can reduce the cross color noise (rainbow-like color smearing) and cross luminance (dot) noise that is generated when a decoder (such as a 3-line decoder) other than 3D YC separator decoder is used for NTSC input. This function makes it possible to produce clear and vivid video with no color blotting and no dot interference. 3. Image quality adjustment block The LC749450NW provides a full complement of image quality adjustment functions and can perform the image quality adjustments required for optimal flat panel TV display. (1) Horizontal outline correction (LTI/CTI) The LTI/CTI block applies outline correction to the input signal. The apparent sharpness in the video image is enhanced by increasing the slope of the input signal. Since this function does not add overshoot or undershoot to edges in the video signal, it creates natural-looking images. This function operates independently on the luminance and chrominance signals. (2) Sharpness (horizontal and vertical) The sharpness function can correct the outlines in the input signal. This function differs from the LTI/CTI function described above in that it adds an appropriate peak in the corrected outline area. The amount of this peak and a coring level that prevents fine noise from being aggravated can be set in the control registers for this circuit. This function only operates on the luminance signal. (3) Shadow adjuster The shadow adjuster function detects the outlines in the input signal and adds an appropriate peak before and after the outline to add an appearance of a shadow. This creates a video signal that is varied and not dull. (4) White and black expansion The white and black expansion function adaptively expands the white and black levels in the Y component of the YCbCr signal using the white and black peak levels in the immediately preceding field, the luminance signal average picture level (APL), distributional information, and microcontroller settings. The white and black peaks are the maximum and minimum values in the input data within a single field. When the white and black expansion function is used, the values of the settings must be set appropriately. (5) White text correction (blue stretch) The blue stretch function creates visually pleasing white text by adding a small amount of blue to white characters. A gain adjustment is applied to section of the Y signal recognized as white text and added to the Cb signal. (6) Flesh tone correction The flesh tone correction function extracts just the set skin color without affecting other colors and allows just that color to be adjusted. (7) Hues and color gain adjustment The hue adjustment adjusts the hue of the whole image. The color gain adjustment adjusts the depth of the color by controlling the gain applied to the color difference signals. This function can adjust the Cb and Cr signals independently.
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(8) Color exciter The color exciter can independently control the red, green, blue, magenta, yellow, and cyan colors. (9) Brightness and contrast controls The brightness control adjusts the brightness of the screen as a whole and the contrast control adjusts the gain applied to the brightness. (10) White balance and black balance adjustments These adjust the appearance of white and black on the LCD panel. (11) Gamma correction This function allows the creation of arbitrary gamma curves to match the characteristics of the LCD panel used. The RGB channels can be adjusted independently, using internal programmable LUT. (12) Dithering The LC749450NW performs internal signal processing with a 10-bit precision. When these signals are output as 8-bit values, the lower two bits are rounded by dithering. 4. Outputs and Other Functions (1) Matrix conversion The LC749450NW provides the following matrix conversion functions. YCbCr RGB YPbPr RGB YPbPr YCbCr RGB YCbCr (2) Aspect ratio conversion An input Rec.601 signal (example: 720 x 240) can be expanded in the horizontal direction and displayed on a WVGA panel. (3) Output formats The LC749450NW can output video in the following formats. Digital RGB (30 or 24 bits) Digital YCbCr (30 or 24 bits) (4) Clamp control The LC749450NW can generate the clamp signals required for the front-end A/D converter. It can also generate arbitrary pulses (high, low, or high impedance) by comparing with an IC internal threshold value (that can be set with a register setting). (5) SDRAM interface The LC749450NW includes an SDRAM interface that can directly connect either: Two 16 Mbit SDRAMs (512 words x 16 bits x 2 banks) or One 64 Mbit SDRAM (512 words x 32 bits x 4 banks). This allows end product systems to be constructed easily. SDRAMs with a speed grade of 70 or better must be used. (6) I2C bus interface and CPU interface The LC749450NW is basically designed to be controlled by setting internal registers over the I2C bus. The slave address can be switched to match the system by controlling pin 85 (SLADR). The following slave addresses are supported. SLADR = low: E0h SLADR = high: E2h Certain registers can also be controlled over the CPU interface.
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I/O Specifications Input Signals
Signal type Video signals Number of pins 10 10 10 Sync signals 1 1 Data enable signals Pixel clock Fixed oscillator System reset Total 1 1 1 1 1 1 1 40 Symbol YIN CBI CRI DHS DVS DEHI DEVI FIELD CLKI DCLKI XTAL XRST -- System reset -- Y or G Cb or B or C Cr or R or OSD Horizontal sync signal Vertical sync signal Data enable Vertical data enable Field signal input Clock Used for the output dot clock Description Notes NTSC/PAL/DTV (4801, 480P, 1080I) or progressive scan RGB (up to SXGA) or NTSC/PAL decoder input Pixel sync horizontal sync signal input The polarity can be switched by setting the DVPOLIN internal register. Vertical sync signal input The polarity can be switched by setting the DVPOLIN internal register. Valid video period enable signal (horizontal/composite) Valid video period enable signal (vertical) Field signal input System clock input System clock input Fixed clock input or test clock input System reset input, active low --
Output Signals
Signal type Video signals Number of pins 10 10 10 Sync signals 1 1 Data enable signals Pixel clocks Clamp pulse signals Clamp levels 1 1 1 Field discrimination signals Total 39 -- -- -- 1 CLPG CLPB CLPR Y/G clamp level Cb/B clamp level Cr/R clamp level Outputs an odd/even field discrimination signal (Used when IP conversion is not used.) Clamp level discrimination output (Too large: low, too small: high, match: high-impedance) 1 1 CLKOUT CLAMPO Outputs the input clock For A/D conversion The polarity can be inverted. Outputs a pulse signal used for A/D conversion clamp period verification 1 Symbol ODG ODB ODR DHO DVO AREA G B R Horizontal sync signal Vertical sync signal Data enable This pin outputs the DHS pin input after a delay. (Used for pixel sync.) (This can be set over the I2C bus.) Outputs a vertical pixel sync signal. Outputs a valid area signal. Description RGB output The LC749450NW also supports dithered 8-bit output. Notes
ODEVPPO Field discrimination
Control Signals
Signal type I2C bus signals Number of pins 1 1 1 Data output signals XTAL Total 1 5 XTALSW -- -- This signal sets the XTAL clock pin input operation High: The XTAL clock input signal is divided by 2. -- 1 Symbol SDAIO SCLI SLADR OE Description Data bus Bus clock Slave switching Notes Used for setting internal registers and reading out the internal status. The slave address is "1110000+(R/W)". Sets the I2C bus slave address. Normally low, High: E2h, Low: E0h. Data output enable signal
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SDRAM Control Signals
Signal type Clock signals Control system signals Address system signals Data system signals Total Number of pins 1 1 1 1 1 11 1 1 32 50 Symbol SDCLKI SDCLKO SDRAS SDCAS SDWE SAD SDBS SDDQM SDQ -- -- Description SDRAM clock input SDRAM clock output SDRAM row address strobe signal output SDRAM column address strobe signal output SDRAM write enable signal output SDRAM address signal output SDRAM bank select signal output SDRAM data mask signal output SDRAM data input and output -- Notes
Other Signals
Signal type CPU and test signals Number of pins 4 4 8 1 1 1 Symbol GP_ADR1 GP_ADR2 GP_IO GP_WR GP_CS GP_MOD Description GP address input GP address input GP I/O Notes General-purpose parallel bus address input/test setting General-purpose parallel bus address input/test setting General-purpose parallel bus I/O or test circuit outputs General-purpose parallel bus write enable General-purpose parallel bus chip select Internal register control method selection High: Parallel bus mode Low: I2C bus mode 1 GP_TST_SW General-purpose parallel bus I/O or test mode switching High: Parallel bus mode Low: Test mode 6 5 Total 33 TSTI TSTO -- Test input Test output -- Test inputs. These pins are normally left open. Test outputs. These pins are normally left open. --
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LC749450NW Specifications
Absolute Maximum Ragings at VSS = 0 V
Parameter Maximum supply voltage (I/O) Maximum supply voltage (core) Input voltage Output voltage Allowable power dissipation Storage temperature Operating temperature Symbol DVDD33 AVDD33 DVDD18 DPVDD18 VI VO Pd max Tstg Topr Conditions Ratings -0.3 to +3.96 -0.3 to +2.16 -0.5 to 6.0 -0.3 to VDD + 0.3 1 -55 to +125 -30 to +70 Unit V V V V W C C
Allowable Operating Ranges at Ta = -30 to +70C
Parameter Supply voltage (I/O) Supply voltage (core) Input voltage range Symbol DVDD33 VDD18 VIN Conditions Ratings min 3.15 1.71 0 typ 3.3 1.8 max 3.45 1.89 5.5 Unit V V V
Input and Output Pin Capacitance at Ta = 25C, VDD = VI = 0 V
Parameter Input pins Output pins I/O pins Symbol CIN COUT CI/O f = 1 MHz f = 1 MHz f = 1 MHz Conditions Ratings min typ max 10 10 10 Unit pF pF pF
DC Characteristics at Ta = -30 to +70C, VDD33 = 3.15 to 3.45 V, VDD18 = 1.71 to 1.89 V
Parameter High-level input voltage Low-level input voltage High-level input current Low-level input current High-level output voltage Low-level output voltage Output leakage current Pull-down resistor Operating current drain Static current drain *1 guaranteed. Symbol VIH VIL IIH IIL VOH VOL IOZ RDN IDDOP IDDST tck = 135 MHz Outputs open, VI = VSS or VDD 5 V inputs 5 V Schmitt inputs 5 V inputs 5 V Schmitt inputs VI = VDD VI = VDD, with pull-down resistor used VI = VSS T08 type, IOH = -4 mA T12 type, IOH = -8 mA T08 type, IOL = 4 mA T12 type, IOL = 8 mA In the high-impedance output state -10 43 58 500 300 Conditions Ratings min 2.0 1.50 -0.3 -0.3 -10 +10 -10 VDD - 0.8 VDD - 0.8 0.4 0.4 +10 118 typ max 5.5 5.5 0.8 0.90 +10 +100 +10 Unit V V V V A A A V V V V A k mA A
*1: Some input pins have a built-in pull-down resistor. Note that there are thus certain circuit structures for which the static current drain cannot be
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Pin Assignment
156 105
DVDD33 SDA8 SDA7 SDA6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 DVSS18 DVDD18 DVSS33 DVDD33 ODB9 ODB8 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 SDCLKI DVSS33 DVDD33 ODG9 ODG8 ODG7 ODG6 ODG5 ODG4 ODG3 ODG2 ODG1 ODG0 DVSS33 DVDD33 DVSS18 DVDD18 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 DVSS33
157
104
DVSS33 SDA9 SDA10 SDQ0 SDQ1 SDQ2 SDQ3 SDQ4 SDQ5 DVDD33 DVSS33 DVDD18 DVSS18 SDQ6 SDQ7 SDQ8 SDQ9 SDQ10 SDQ11 SDQ12 SDQ13 DVDD33 DVSS33 SDCLKO SDDQM SDRAS SDCAS SDWE SDBS DVDD33 DVSS33 SDQ14 SDQ15 SDQ16 SDQ17 SDQ18 SDQ19 SDQ20 SDQ21 DVDD18 DVSS18 DVDD33 DVSS33 SDQ22 SDQ23 SDQ24 SDQ25 SDQ26 SDQ27 SDQ28 SDQ29 DVDD33 155 160 150 145 140 135 130 125 120 115 110 105 100 DVDD33 CLKOUT CLPB CLPG CLPR CLAMPO TSTO4 TSTO3 DHO DVO TSTO2 DVSS18 DVDD18 FIELD DEVI AREA TSTO1 XTALSW TSTI5 SLADR SCLI SDAIO NC NC DVSS33 DVDD33 OE TSTO0 ODEVFFO GP_TST_SW GP_MOD GP_WR GP_CS GP_IO7 GP_IO6 GP_IO5 GP_IO4 GP_IO3 DVSS18 DVDD18 GP_IO2 GP_IO1 GP_IO0 GP_ADR7 GP_ADR6 GP_ADR5 GP_ADR4 GP_ADR3 GP_ADR2 GP_ADR1 GP_ADR0 DVSS33 53
165
95
170
90
175
85
180
LC749450NW
185
80
75
190
70
195
65
200
60
205 5 10 15 20 25 30 35 40 45 50
55
208
1
DVSS33 CRI0 CRI1 CRI2 CRI3 CRI4 CRI5 CRI6 CRI7 CRI8 CRI9 DVDD18 DVSS18 YIN0 YIN1 YIN2 YIN3 YIN4 YIN5 YIN6 YIN7 YIN8 YIN9 TSTI0 DHS TSTI1 DVS TSTI2 CLKI DCLKI DEHI TSTI3 TSTI4 XTAL XRST DVDD18 DVSS18 CBI0 CBI1 CBI2 CBI3 CBI4 CBI5 CBI6 CBI7 CBI8 CBI9 DPVDD18 DPVSS18 AVDD33 AVSS33 DVDD33
52 Top view
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Pin Listing
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Symbol DVSS33 CRI0 CRI1 CRI2 CRI3 CRI4 CRI5 CRI6 CRI7 CRI8 CRI9 DVDD18 DVSS18 YIN0 YIN1 YIN2 YIN3 YIN4 YIN5 YIN6 YIN7 YIN8 YIN9 TSTI0 DHS TSTI1 DVS TSTI2 CLKI DCLKI DEHI TSTI3 TSTI4 XTAL XRST DVDD18 DVSS18 CBI0 CBI1 CBI2 CBI3 CBI4 CBI5 CBI6 CBI7 CBI8 CBI9 DPVDD18 DPVSS18 AVDD33 AVSS33 DVDD33 DVSS33 GP_ADR0 GP_ADR1 GP_ADR2 GP_ADR3 GP_ADR4 GP_ADR5 GP_ADR6 GP_ADR7 I/O circuit type I/O P I I I I I I I I I I P P I I I I I I I I I I I I I I I I I I I I I I P P I I I I I I I I I I P P P P P P I I I I I I I I PHICD CPU address input or Test mode subsidiary setting inputs -- -- -- -- -- -- Power supply GND Power supply GND Power supply GND PLL 1.8 V digital system power supply PLL 1.8 V digital system ground PLL 3.3 V analog system power supply PLL 3.3 V analog system ground 3.3 V system power supply 3.3 V system ground PHICD Digital interface Cb/B signal input PHICD PHICD PHICD PHICD PHISD PHIC PHIC PHICD PHISD PHICD PHIC PHIS -- -- Initialization circuit Power supply GND Open Open Open Open Open Test input. This pin is normally left open. Horizontal sync signal (The polarity can be switched.) Test input. This pin is normally left open. Vertical sync signal (The polarity can be switched.) Test input. This pin is normally left open. System clock System clock Valid video period enable signal input Test input. This pin is normally left open. Test input. This pin is normally left open. Fixed clock connection System reset (Reset on a low-level input) 1.8 V system power supply 1.8 V system ground PHICD Digital interface Y/G signal input RT.656 input -- -- Power supply GND 1.8 V system power supply 1.8 V system ground PHICD Digital interface Cr/R signal input Circuit type -- Connected to GND 3.3 V system ground Notes
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Pin No. 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 Symbol GP_IO0 GP_IO1 GP_IO2 DVDD18 DVSS18 GP_IO3 GP_IO4 GP_IO5 GP_IO6 GP_IO7 GP_CS GP_WR GP_MOD CPU_TST_SW ODEVFFO TSTO0 OE DVDDD33 DVSS33 NC NC SDAIO SCLI SLADR TST15 XTALSW TSTO1 AREAO DEVI FIELD DVDD18 DVSS18 TSTO2 DVO DHO TSTO3 TSTO4 CLAMPOO CLPR CLPG CLPB CLKOUT DVDD33 DVSS33 ODR0 ODR1 ODR2 ODR3 ODR4 ODR5 ODR6 ODR7 ODR8 ODR9 DVDD18 DVSS18 DVDD33 DVSS33 I/O circuit type I/O B B B P P B B B B B I I I I O O I P P -- -- B I I I I O O I I P P O O O O O O O O O O P P O O O O O O O O O O P P P P -- -- -- -- Power supply GND Power supply GND 1.8 V system power supply 1.8 V system ground 3.3 V system power supply 3.3 V system ground PHOT08 R signal outputs PHICD PHICD PHICD PHISD PHOT08 PHOT12 PHISD -- -- -- -- PHBT12 PHISD PHISD PHISD PHISD PHOT08 PHOT08 PHICD PHICD -- -- PHOT08 PHOT08 PHOT08 PHOT08 PHOT08 PHOT08 PHOT12 PHOT12 PHOT12 PHOT12 -- -- Power supply GND Open Open Power supply GND Open Open Open Power supply GND Open Open Open CPU bus chip enable input CPU bus write enable input CPU bus mode switch CPU/test mode switch Field discrimination signal output Test output. This pin is normally left open. Output enable 3.3 V system power supply 3.3 V system ground No connection No connection I2C bus data I/O I2C bus clock input I2C bus slave address setting Test input. This pin is normally left open. XTAL clock pin input mode setting input Test output. This pin is normally left open. Valid area signal output Vertical valid video period enable signal input Field signal input 1.8 V system power supply 1.8 V system ground Test output. This pin is normally left open. Vertical sync signal output (The polarity can be switched.) Horizontal sync signal output (The polarity can be switched.) Test output. This pin is normally left open. Test output. This pin is normally left open. A/D conversion clamp period verification pulse output Clamp control output (R/Cr) Clamp control output (G/Y) Clamp control output (B/Cb) Clock output 3.3 V system power supply 3.3 V system ground PHBT08 CPU I/O or Test circuit outputs -- -- Power supply GND PHBT08 Circuit type Connected to CPU I/O or Test circuit outputs 1.8 V system power supply 1.8 V system ground Notes
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Pin No. 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 Symbol ODG0 ODG1 ODG2 ODG3 ODG4 ODG5 ODG6 ODG7 ODG8 ODG9 DVDD33 DVSS33 SDCLKI ODB0 ODB1 ODB2 ODB3 ODB4 ODB5 ODB6 ODB7 ODB8 ODB9 DVDD33 DVSS33 DVDD18 DVSS18 SAD0 SAD1 SAD2 SAD3 SAD4 SAD5 SAD6 SAD7 SAD8 DVDD33 DVSS33 SAD9 SAD10 SDQ0 SDQ1 SDQ2 SDQ3 SDQ4 SDQ5 DVDD33 DVSS33 DVDD18 DVSS18 SDQ6 SDQ7 SDQ8 SDQ9 SDQ10 SDQ11 SDQ12 SDQ13 DVDD33 DVSS33 I/O circuit type I/O O O O O O O O O O O P P I O O O O O O O O O O P P P P O O O O O O O O O P P O O B B B B B B P P P P B B B B B B B B P P -- -- Power supply GND 3.3 V system power supply 3.3 V system ground PHBT12 SDRAM clock output -- -- -- -- Power supply GND Power supply GND 3.3 V system power supply 3.3 V system ground 1.8 V system power supply 1.8 V system ground PHBT12 SDRAM data I/O -- -- PHOT12 Power supply GND 3.3 V system power supply 3.3 V system ground SDRAM address outputs PHOT12 SDRAM address outputs -- -- -- -- Power supply GND Power supply GND 3.3 V system power supply 3.3 V system ground 1.8 V system power supply 1.8 V system ground PHOT08 B signal outputs -- -- PHIC Power supply GND 3.3 V system power supply 3.3 V system ground SDRAM system clock PHOT08 G signal outputs Circuit type Connected to Notes
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Pin No. 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Symbol SDCLKO SDDQM SDRAS SDCAS SDWE SDBS DVDD33 DVSS33 SDQ14 SDQ15 SDQ16 SDQ17 SDQ18 SDQ19 SDQ20 SDQ21 DVDD18 DVSS18 DVDD33 DVSS33 SDQ22 SDQ23 SDQ24 SDQ25 SDQ26 SDQ27 SDQ28 SDQ29 DVDD33 I/O circuit type I/O O O O O O O P P B B B B B B B B P P P P B B B B B B B B P -- Power supply 3.3 V system power supply PHBT12 SDRAM data I/O -- -- -- -- Power supply GND Power supply GND 1.8 V system power supply 1.8 V system ground 3.3 V system power supply 3.3 V system ground PHBT12 SDRAM clock output Circuit type PHOT12 PHOT12 PHOT12 PHOT12 PHOT12 PHOT12 -- -- Power supply GND Connected to SDRAM clock output SDRAM data mask output SDRAM row address strobe output SDRAM column address strobe output SDRAM write enable output SDRAM bank select output 3.3 V system power supply 3.3 V system ground Notes
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Pin Circuits
I/O type Function Applicable pins Equivalent circuit
PHIC
5 V input
CLKI, DCLKI, XTALI, SDCLKI
PHIS
5 V Schmitt input
XRST
PHICD
5 V pull-down resistor input
YIN0 to 9, CBI0 to 9, CRI0 to 9, GP_ADR0 to 7, DEHI, DEVI, DHS, DVS, FIELD, GP_CS, GP_WR, GP_MOD, TSTI0, TSTI1, TSTI4
PHISD
5 V pull-down resistor Schmitt input
XTAL_SW, SCLI, SLADR, OE, CPU_TST_SW, TSTI2, TSTI3, TSTI5
PHOT08
8 mA 3-state drive output 8 mA 3-state drive output 12 mA 3-state drive output
ODR0 to 9, ODG0 to 9, ODB0 to 9, DHO, DVO, ODEVFFO, CLAMPOO, AREAO, TSTO1 to 4 CLPB, CLPG, CLPR CLKOUT, SAD0 to 10, SDCLKO, SDRAS, SDCAS, SDWE, SDDQM, SDBS, TSTO0
POT08
PHOT12
PHBT08
8 mA 3-state drive I/O
GP_IO0 to 7
PHBT12
12 mA 3-state drive I/O SDQ0 to 29, SDAIO
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Input and Output Data Timing (1) Input Data Timing 1
tHI CLKI tSU tHD Input data VDD33/2 t LO t CK VDD33/2
Parameter Clock low-level time Clock high-level time Clock period Input data setup time Input data hold time
Symbol tLO tHI tCK tSU tHD CLKI
Pins
min 3.70 3.70 7.40 2.5 0.5
max -- -- -- -- --
Unit ns ns ns ns ns
YIN [9:0], CBI [9:0], CRI [9:0], DHS, DVS, DEHI, DEVI, FIELD
*: We recommend a duty of 50% for the input clock.
(2) Input Data Timing 2
tHI SDCLKI tSU tHD Input data VDD33/2 tLO tCK VDD33/2
Parameter Clock low-level time Clock high-level time Clock period Input data setup time Input data hold time
Symbol tLO tHI tCK tSU tHD SDCLKI
Pins
min 3.70 3.70 7.40 2 1
max -- -- -- -- --
Unit ns ns ns ns ns
SDRAS, SDCAS, SDWE, SAD [10:0], SDBS, SDQ [29:0]
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(3) Output Data Timing 1
tHI CLKOUT tAC tHD Output data VDD33/2 tLO tCK VDD33/2
Parameter Clock low-level time Clock high-level time Clock period Output data delay time Input data hold time
Symbol tLO tHI tCK tAC tHD CLKOUT
Pins
min 3.70 3.70 7.40 -1.5 5.90
max -- -- -- 1.5 --
Unit ns ns ns ns ns
ODR [9:0], ODG [9:0], ODB [9:0], DHO, DVO, AREA
(4) Output Data Timing 2
tHI SDCLKO tCK VDD33/2 tAC tHD Output data tLO
VDD33/2
Parameter Clock low-level time Clock high-level time Clock period Output data delay time Input data hold time
Symbol tLO tHI tCK tAC tHD SDQ [29:0] SDCLKO
Pins
min 3.70 3.70 7.40 -1.0 4
max -- -- -- 1.0 --
Unit ns ns ns ns ns
No.8096-15/17
LC749450NW
I/O Clock Timing (1) Input System Clock Timing
tHI Input CLKI tOUT Output CLKOUT tOUT Output SDCLKO VDD33/2 tLO VDD33/2 tCK VDD33/2
Parameter Clock low-level time Clock high-level time Clock period CLKOUT delay time SDCLK delay time
Symbol tLO tHI tCK tOUT tOUT CLKOUT SDCLKO CLKI
Pins
min 3.70 3.70 7.40 4 4
max -- -- -- 17 17
Unit ns ns ns ns ns
Block Diagram
Line Memory
Line Memory
Y/G/YY 10 Cb/B/CC 10 Cr/R 10 Input signal format conversion YUV matrix IP conversion Motion detection Cinema detection Noise reduction
Image quality adjustments 1
White/black expansion White text correction (blue stretch) Outline correction Shadow adjuster Hue correction Flesh tone correction Color gain Color exciter RGB Matrix
Image quality adjustments 2
White balance Contrast Black balance Brightness Gamma correction Gray scale conversion
G/Y 10 B/Cb 10 R/Cr 10
CLK PLL SDRAM Interface I2C Interface
DQn
30
I2C bus
2
No.8096-16/17
LC749450NW
Application Circuit Example
DVI
DVI receiver SDRAM 16Mbx2 or 64Mbx1
YCbCr GBR
ADC
LC749450NW
Scaler
Flat panel monitor
CVBS Y/C
Video decoder
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the author ities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of July, 2005. Specifications and information herein are subject to change without notice.
PS No.8096-17/17

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